Ebook Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC), by Sridhar Gangadharan, Sa
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Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC), by Sridhar Gangadharan, Sa
Ebook Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC), by Sridhar Gangadharan, Sa
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This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.
- Sales Rank: #286029 in Books
- Published on: 2013-05-07
- Original language: English
- Number of items: 1
- Dimensions: 9.21" h x .63" w x 6.14" l, 1.18 pounds
- Binding: Hardcover
- 226 pages
From the Back Cover
This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.
· Provides a hands-on guide to synthesis and timing analysis, using Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints;
· Includes key topics of interest to a synthesis, static timing analysis or place and route engineer;
· Explains which constraints command to use for ease of maintenance and reuse, given several options possible to achieve the same effect on timing;
· Explains fundamental concepts and provides exact command syntax.
About the Author
Sanjay Churiwala is an Electronics Engineer from IIT Kharagpur, with two decades of experience in EDA and VLSI. His interest areas include rule checking, synthesis, simulation, STA, Power and Clock Domain Crossings and Synchronization. He currently works at Hyderabad office of Xilinx.
Sridhar Gangadharan is a Senior Product Engineering Director for Timing Constraints Analysis and SpyGlass RTL Analysis Products at Atrenta. He has over 20 years of experience in the electronic design automation industry. His interest areas include RTL verification, timing closure, delay calculation and memory compilers. He holds a Bachelors degree in Computer Science and Engineering from Indian Institute of Technology in Delhi. He is based in San Jose, CA.
Most helpful customer reviews
3 of 4 people found the following review helpful.
I was very disappointed with this book
By Amazon Customer
I was very disappointed with this book, considering the price. I was hoping for some more detailed real world examples. The level of detail presented can just be found with some simple google searching.
0 of 0 people found the following review helpful.
Good book
By Noorav
This is a very practical book written from point of view of mainly synthesis and less focus on physical design aspects. Though the book lacks detailed theory about timing analysis(parasitic modeling, extraction etc.), however I think information goen is still enough information to start writing tcl design constraints in sdc file. This book actually fills the gap that most theory oriented STA books usually donot capture.
3 of 4 people found the following review helpful.
The go-to handbook for Synopsys Design Constraints
By Satrajit Pal
An excellent handbook for Synopsys Design Constraints (SDC). The context in which the SDCs are typically used is nicely explained. It becomes very useful for people like me (EDA engineers) who have to understand how the designers use the Constraints in their world. Most material on SDCs are about the different options that a particular SDC has, but never explains clearly why one might use the option.
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